Technical Field
The present invention generally relates to nanosheet field effect transistors and, more particularly, to the use of air-gap inner and outer spacers in such transistors.
Description of the Related Art
One design challenge in the fabrication of gate-all-around nanosheet field effect transistors (FETs) is the reduction of parasitic capacitance between gate and source/drain regions. Parasitic capacitance is of particular concern in alternating current applications, where reactive impedances can cause spurious oscillations.
Dielectric spacers are used to diminish parasitic capacitance, and air-gap spacers have particularly useful properties toward this end. However, conventional air-gap spacer formation relies on the non-conformal deposition of dielectric material and etch-back processes, which are difficult to control precisely and which lead to variation and non-uniformity in the air gaps.